A testability-driven optimizer and wrapper generator for embedded memories

Rei Fu Huang, Li Ming Denq, Cheng Wen Wu, Jin Fu Li

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation-a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial memory compiler. We describe one of its key components called MORE (for Memory Optimization and REconfiguration). The approach is cost effective for designing embedded memories. By configuring small memory cores into the large one specified by the user and providing the BIST circuits, MORE allows the user to combine the commercial memory compiler and our memory BIST compiler into a cost-effective testability-driven memory generator. The resulting memory has a shorter test time, since the small memory cores can be tested in parallel, so far as the power and geometry constraints are considered. As an example, the test time of a typical 256K×32 memory generated by MORE is reduced by about 75%.

原文English
主出版物標題Records of the 2003 International Workshop on Memory Technology, Design and Testing, MTDT 2003
發行者IEEE Computer Society
頁面53-56
頁數4
ISBN(電子)0769520049
DOIs
出版狀態Published - 2003 一月 1
事件Records of the 2003 International Workshop on Memory Technology, Design and Testing, MTDT 2003 - San Jose, United States
持續時間: 2003 七月 282003 七月 29

出版系列

名字Records of the IEEE International Workshop on Memory Technology, Design and Testing
2003-January
ISSN(列印)1087-4852

Conference

ConferenceRecords of the 2003 International Workshop on Memory Technology, Design and Testing, MTDT 2003
國家/地區United States
城市San Jose
期間03-07-2803-07-29

All Science Journal Classification (ASJC) codes

  • 媒體技術

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