A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Liang Ying Lu, Ching Yao Chang, Zhao Hong Chen, Bo Ting Yeh, Tai Hua Lu, Peng Yu Chen, Pin Hao Tang, Kuen Jong Lee, Lih Yih Chiou, Soon Jyh Chang, Chien Hung Tsai, Chung Ho Chen, Jai Ming Lin

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

原文English
主出版物標題2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面17-18
頁數2
ISBN(電子)9781467395694
DOIs
出版狀態Published - 2016 三月 7
事件21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
持續時間: 2016 一月 252016 一月 28

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
國家Macao
城市Macao
期間16-01-2516-01-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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