This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.