A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

Hung Yuan Chu, Chun Hung Yang, Chi Wai Leng, Chien Hung Tsai

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

原文English
主出版物標題Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
頁面1390-1393
頁數4
DOIs
出版狀態Published - 2008
事件APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
持續時間: 2008 十一月 302008 十二月 3

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
國家/地區China
城市Macao
期間08-11-3008-12-03

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A」主題。共同形成了獨特的指紋。

引用此