A unified test and debug platform for SOC design

Kuen-Jong Lee, Chin Yao Chang, Alan Su, Si Yuan Liang

研究成果: Conference contribution

1 引文 (Scopus)

摘要

As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

原文English
主出版物標題ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
頁面577-580
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
持續時間: 2009 十月 202009 十月 23

出版系列

名字ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
國家China
城市Changsha
期間09-10-2009-10-23

指紋

Built-in self test
Testing
Silicon
Failure analysis
Hardware
Economics
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

Lee, K-J., Chang, C. Y., Su, A., & Liang, S. Y. (2009). A unified test and debug platform for SOC design. 於 ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (頁 577-580). [5351351] (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351351
Lee, Kuen-Jong ; Chang, Chin Yao ; Su, Alan ; Liang, Si Yuan. / A unified test and debug platform for SOC design. ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. 頁 577-580 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).
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abstract = "As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.",
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Lee, K-J, Chang, CY, Su, A & Liang, SY 2009, A unified test and debug platform for SOC design. 於 ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351351, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 頁 577-580, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 09-10-20. https://doi.org/10.1109/ASICON.2009.5351351

A unified test and debug platform for SOC design. / Lee, Kuen-Jong; Chang, Chin Yao; Su, Alan; Liang, Si Yuan.

ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 577-580 5351351 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

研究成果: Conference contribution

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AB - As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

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Lee K-J, Chang CY, Su A, Liang SY. A unified test and debug platform for SOC design. 於 ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 577-580. 5351351. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351351