A universal March pattern generator for testing embedded memory cores

Wei Lun Wang, Kuen Jong Lee, Jhing Fa Wang

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

原文English
主出版物標題Proceedings - 12th Annual IEEE International ASIC/SOC Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面228-232
頁數5
ISBN(電子)0780356322, 9780780356320
DOIs
出版狀態Published - 1999
事件12th Annual IEEE International ASIC/SOC Conference - Washington, United States
持續時間: 1999 九月 151999 九月 18

出版系列

名字Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Other

Other12th Annual IEEE International ASIC/SOC Conference
國家/地區United States
城市Washington
期間99-09-1599-09-18

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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