A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

Lih Yih Chiou, Chi Ray Huang, Chang Chieh Cheng, Jing Yu Huang, Wei Suo Ling

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

原文English
主出版物標題2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728106557
DOIs
出版狀態Published - 2019 4月
事件2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
持續時間: 2019 4月 222019 4月 25

出版系列

名字2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
國家/地區Taiwan
城市Hsinchu
期間19-04-2219-04-25

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 儀器
  • 電腦網路與通信
  • 硬體和架構

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