A wideband CMOS sigma-delta modulator with incremental data weighted averaging

Tai Haur Kuo, Kuan Dar Chen, Horng Ru Yeng

研究成果: Article同行評審

78 引文 斯高帕斯(Scopus)


A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low over-sampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dispissation is less than 105 mW and the active area is 2.6 mm2. Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

頁(從 - 到)11-17
期刊IEEE Journal of Solid-State Circuits
出版狀態Published - 2002 一月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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