A word-based RSA crypto-processor with enhanced pipeline performance

Chen Hsing Wang, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

We propose a high speed RSA crypto-processor based on an enhanced word-based Montgomery Multiplication (MM) algorithm. With the help of the proposed Correction Module (CM), the word-based modular multiplier can achieve 100% utilization. A simplified Parity Trediction Module (PPM) is also proposed to eliminate the pipeline stall. Using a 0.18μm CMOS standard cell library, our RSA crypto-processor achieves a 512-bit RSA encryption rate of 3/5Kbps under 300MHz clock. The result shows that our architecture is cost-effective in terms of area and performance.

原文English
主出版物標題Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
頁面218-221
頁數4
出版狀態Published - 2004 十二月 1
事件Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
持續時間: 2004 八月 42004 八月 5

出版系列

名字Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
國家Japan
城市Fukuoka
期間04-08-0404-08-05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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