AC-plus scan methodology for small delay testing and characterization

Tsung Yeh Li, Shi Yu Huang, Hsuan Jung Hsu, Chao Wen Tzeng, Chih Tsun Huang, Jing Jia Liou, Hsi Pin Ma, Po Chiun Huang, Jenn Chyou Bor, Ching Cheng Tien, Chih Hu Wang, Cheng Wen Wu

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)


Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability.

頁(從 - 到)329-341
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版狀態Published - 2013 一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程


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