Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Rizwan Bashirullah, Wentai Liu, Ralph Cavin

研究成果: Conference article同行評審

摘要

A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6μm is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long on-chip interconnects.

原文English
頁(從 - 到)V169-V172
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
出版狀態Published - 2003
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 2003 5月 252003 5月 28

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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