Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations

Shi Xuan Zheng, Chung Yu Yeh, Kuen Jong Lee, Chen Wang, Wu Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy

研究成果: Conference contribution


Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

主出版物標題Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022
發行者IEEE Computer Society
出版狀態Published - 2022
事件40th IEEE VLSI Test Symposium, VTS 2022 - Virtual, Online, United States
持續時間: 2022 4月 252022 4月 27


名字Proceedings of the IEEE VLSI Test Symposium


Conference40th IEEE VLSI Test Symposium, VTS 2022
國家/地區United States
城市Virtual, Online

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程


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