Address compression for scalable load/store queue implementation

Yi Ying Tsai, Chia Jung Hsu, Chung-Ho Chen

研究成果: Conference contribution

摘要

Contemporary superscalar processors employ the load/store queue for memory disambiguation. A load/store queue is typically implemented with a CAM structure to search the address for collision and consequently poses scalability challenges of energy consumption and area cost. This paper proposes an address compression technique for load/store queue to improve the power efficiency and scalability. Using the proposed approach, the LSQ can reduce the energy consumption ranging from 38% to 72% and area cost ranging from 32% to 66%, depending on the compression parameter and system configuration. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at a balanced configuration.

原文English
主出版物標題2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
頁面1680-1683
頁數4
DOIs
出版狀態Published - 2008 9月 19
事件2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
持續時間: 2008 5月 182008 5月 21

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
國家/地區United States
城市Seattle, WA
期間08-05-1808-05-21

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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