Advanced low damage manufacturing processes to fabricate SOI FinFETs and measurement of electrical properties

Ashish Kumar, Wen Hsi Lee, Y. L. Wang

研究成果: Article同行評審

摘要

In this paper, FinFETs are realized by integrating neutral beam etching(NBE) and microwave annealing (MWA) into the fabrication process. Electrical characteristics are measured at room temperature and parameters such as Sub-threshold swing of 89 mV/decade, Ion/Ioff of 106, DIBL of 72 mV/V and effective mobility (μeff) of 502 cm2V−1 s−1 are obtained with Wfin/Lgate = 40/100 nm. These characteristics are superior by using neutral beam etching than by using RIE-like condition, and the Vt shift at reduced Lgate is also suppressed. A damaged layer at high-k/Si interface by RIE-like condition is observed in the TEM image, which can correspond to the degradation in electrical characteristics. Furthermore, the proportional scaling of Ion versus Wfin indicates negligible S/D resistance due to good activation by Microwave annealing (MWA). In short, functional FinFETs were fabricated by Neutral beam etching (NBE) and Microwave annealing (MWA) for the first time, and these results pave ways for the techniques to be adopted in the advanced semiconductor processing. The SOI FinFETs demonstrate proportional scaling of on current versus the fin width and indicating that the S/D region is well activated by the microwave annealing method.

原文English
文章編號114115
期刊Microelectronics Reliability
120
DOIs
出版狀態Published - 2021 5月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 安全、風險、可靠性和品質
  • 表面、塗料和薄膜
  • 電氣與電子工程

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