AF-test: Adaptive-frequency scan test methodology for small-delay defects

Tsung Yeh Li, Shi Yu Huang, Hsuan Jung Hsu, Chao Wen Tzeng, Chih Tsun Huang, Jing Jia Liou, Hsi Pin Ma, Po Chiun Huang, Jenn Chyou Bor, Cheng Wen Wu, Ching Cheng Tien, Mike Wang

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis [14], we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.

原文English
主出版物標題Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
頁面340-348
頁數9
DOIs
出版狀態Published - 2010 十二月 1
事件2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 - Kyoto, Japan
持續時間: 2010 十月 62010 十月 8

出版系列

名字Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN(列印)1550-5774

Conference

Conference2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
國家Japan
城市Kyoto
期間10-10-0610-10-08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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