All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Tzuen-Hsi Huang, Hong Yi Huang, Jen Chieh Liu, Kuo Hsing Cheng, Ching Hsing Luo

研究成果: Conference contribution

摘要

A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um2. The power consumption is 5.4 mW at 416 MHz.

原文English
主出版物標題2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
頁面486-489
頁數4
DOIs
出版狀態Published - 2011
事件2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
持續時間: 2011 五月 152011 五月 18

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
國家Brazil
城市Rio de Janeiro
期間11-05-1511-05-18

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • 引用此

    Huang, T-H., Huang, H. Y., Liu, J. C., Cheng, K. H., & Luo, C. H. (2011). All digital phase-locked loop using active inductor oscillator and novel locking algorithm. 於 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (頁 486-489). [5937608] https://doi.org/10.1109/ISCAS.2011.5937608