This work presents a high-speed low-power subranging analog-to-digital converter (ADC). The prototype achieves a subranging operation with a level-shift operation technique, which has a higher speed compared with the conventional subranging architecture. A background calibration is proposed to overcome the non-idealities from the level-shift circuit. With the above techniques, an 8-bit 1.5GS/s subranging ADC is implemented in 90nm CMOS technology and the active area occupies 0.192mm2. With the post-layout simulation, the ADC consumes 17mW at 1.5GS/s from a 1V supply and the signal-to-noise-and-distortion ratio (SNDR) is 45.6dB with Nyquist frequency input. The ADC has a Walden Figure-of-Merit (FOMW) of 72.8fJ/conv-step, which is comparable to prior state-of-the-art 8-bit high-speed ADCs. Furthermore, this ADC achieves the highest operation speed compared with the subranging ADCs.