An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator

Chih Huei Hou, Soon Jyh Chang, Hao Sheng Wu, Huan Jui Hu, En Ze Cun

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

A single-channel lb/cycle 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The operation speed is enhanced by using the loop-unrolled technique in the coarse conversions. Moreover, we propose a timing control scheme which would shorten the critical timing path to alleviate the speed limitation in the fine conversions. Also, we propose a high-gain dynamic pre-amplifier to realize such a timing control scheme so as to meet our target resolution. The proof-of-concept prototype was fabricated in a TSMC 90-nm CMOS technology. At 1.2-V supply voltage and 400-MS/s sampling rate, the power consumption of the SAR ADC is 3.198 mW. The peak ENOB is 7.15 bits without costly calibration circuit. It achieves a figure of merit (FoM) of 56.29 fJ/conversion-step.

原文English
主出版物標題2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509039692
DOIs
出版狀態Published - 2017 6月 5
事件2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
持續時間: 2017 4月 242017 4月 27

出版系列

名字2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Other

Other2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
國家/地區Taiwan
城市Hsinchu
期間17-04-2417-04-27

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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