A single-channel lb/cycle 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The operation speed is enhanced by using the loop-unrolled technique in the coarse conversions. Moreover, we propose a timing control scheme which would shorten the critical timing path to alleviate the speed limitation in the fine conversions. Also, we propose a high-gain dynamic pre-amplifier to realize such a timing control scheme so as to meet our target resolution. The proof-of-concept prototype was fabricated in a TSMC 90-nm CMOS technology. At 1.2-V supply voltage and 400-MS/s sampling rate, the power consumption of the SAR ADC is 3.198 mW. The peak ENOB is 7.15 bits without costly calibration circuit. It achieves a figure of merit (FoM) of 56.29 fJ/conversion-step.