TY - GEN
T1 - An adaptive code rate EDAC scheme for random access memory
AU - Chen, Ching Yi
AU - Wu, Cheng Wen
PY - 2010/6/9
Y1 - 2010/6/9
N2 - As the VLSI technology scaling continues and the device dimension keeps shrinking, memories are more and more sensitive to soft errors. Memory cores usually occupy a large portion of an SOC and have significant impact on the chip reliability. Therefore error detection and correction (EDAC) techniques are commonly used for protecting the system against soft errors. This paper presents a novel EDAC scheme, which provides adaptive code rate for random access memories (RAMs). Under a certain reliability restriction, the proposed design allows more error bits than a conventional EDAC design.
AB - As the VLSI technology scaling continues and the device dimension keeps shrinking, memories are more and more sensitive to soft errors. Memory cores usually occupy a large portion of an SOC and have significant impact on the chip reliability. Therefore error detection and correction (EDAC) techniques are commonly used for protecting the system against soft errors. This paper presents a novel EDAC scheme, which provides adaptive code rate for random access memories (RAMs). Under a certain reliability restriction, the proposed design allows more error bits than a conventional EDAC design.
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M3 - Conference contribution
AN - SCOPUS:77953108207
SN - 9783981080162
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 735
EP - 740
BT - DATE 10 - Design, Automation and Test in Europe
T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Y2 - 8 March 2010 through 12 March 2010
ER -