An adaptive code rate EDAC scheme for random access memory

Ching Yi Chen, Cheng Wen Wu

研究成果: Conference contribution

10 引文 斯高帕斯(Scopus)

摘要

As the VLSI technology scaling continues and the device dimension keeps shrinking, memories are more and more sensitive to soft errors. Memory cores usually occupy a large portion of an SOC and have significant impact on the chip reliability. Therefore error detection and correction (EDAC) techniques are commonly used for protecting the system against soft errors. This paper presents a novel EDAC scheme, which provides adaptive code rate for random access memories (RAMs). Under a certain reliability restriction, the proposed design allows more error bits than a conventional EDAC design.

原文English
主出版物標題DATE 10 - Design, Automation and Test in Europe
頁面735-740
頁數6
出版狀態Published - 2010 六月 9
事件Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
持續時間: 2010 三月 82010 三月 12

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
ISSN(列印)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
國家Germany
城市Dresden
期間10-03-0810-03-12

All Science Journal Classification (ASJC) codes

  • Engineering(all)

指紋 深入研究「An adaptive code rate EDAC scheme for random access memory」主題。共同形成了獨特的指紋。

引用此