An advanced video and depth depacking architecture for 3D applications

Pin Chen Kuo, An Jie Lin, Bin Da Liu, Jar Ferr Yang

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)


In this paper, a first hardware design for the 2D-compatible format and an architecture for the depth-image-based rendering (DIBR) is proposed. Compared to the format that uses one view plus one depth, the advanced 2D-compatible format reduces the bitrates of both color and depth frames. In order to achieve 3D image generation in real time, a hardware architecture of 2D-compatible format is firstly designed in this paper. In this paper, an edge-based DIBR algorithm is also proposed and implemented in to hardware architecture. The proposed edge-based DIBR algorithm achieves better image quality than the original DIBR algorithm. This paper combines these two architecture in to the advanced video and depth depacking architecture which can reduce the bitrates and increase the image quality of 3D video. Simulation results also show that image quality of the proposed system is better than that of the original DIBR algorithm. For the hardware cost, the proposed system requires 6.34k gates. The operation frequency can reach 100 MHz, which can supports the maximum frame size up to FHD (1920 × 1088) in real time.

頁(從 - 到)1537-1555
期刊Journal of Information Science and Engineering
出版狀態Published - 2015 9月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 人機介面
  • 硬體和架構
  • 圖書館與資訊科學
  • 計算機理論與數學


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