TY - GEN
T1 - An all-digital phase-locked loop for digital power management integrated chips
AU - Chung, Yu Ming
AU - Wei, Chia-Ling
PY - 2009/10/26
Y1 - 2009/10/26
N2 - An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-□, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-μm CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz.
AB - An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-□, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-μm CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz.
UR - http://www.scopus.com/inward/record.url?scp=70350140527&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2009.5118287
DO - 10.1109/ISCAS.2009.5118287
M3 - Conference contribution
AN - SCOPUS:70350140527
SN - 9781424438280
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2413
EP - 2416
BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Y2 - 24 May 2009 through 27 May 2009
ER -