An application-independent delay testing methodology for Island-style FPGA

Yen Lin Peng, Jing Jia Liou, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA. And the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time.

原文English
主出版物標題Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
編輯R. Aitken, A. Salsano, R. Velazco, X. Sun
頁面478-486
頁數9
DOIs
出版狀態Published - 2004 十二月 1
事件19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Cannes, France
持續時間: 2004 十月 102004 十月 13

出版系列

名字IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN(列印)1550-5774

Conference

Conference19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
國家France
城市Cannes
期間04-10-1004-10-13

All Science Journal Classification (ASJC) codes

  • Engineering(all)

指紋 深入研究「An application-independent delay testing methodology for Island-style FPGA」主題。共同形成了獨特的指紋。

  • 引用此

    Peng, Y. L., Liou, J. J., Huang, C. T., & Wu, C. W. (2004). An application-independent delay testing methodology for Island-style FPGA. 於 R. Aitken, A. Salsano, R. Velazco, & X. Sun (編輯), Proceedings - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (頁 478-486). (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFTVS.2004.1347873