@inproceedings{319f2b71e4c24b69a08d42b427c2e4ba,
title = "An area- and power-efficient half-rate clock and data recovery circuit",
abstract = "This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor reduces the power consumption and area in high-speed operation. This CDR circuit has been designed in TSMC 0.18 μm CMOS technology. It consumes 22.5 mW from a 1.8-V supply and occupies an active area of 0.26 mm 2. The peak-to-peak and rms jitter of the recovered clock are 95.6 ps and 12.1 ps for a 3.2 Gb/s 27-1 PRBS, respectively.",
author = "Lee, {Yen Long} and Chang, {Soon Jyh} and Chu, {Rong Sing} and Chen, {Yen Chi} and Goh, {Jih Ren} and Huang, {Chung Ming}",
year = "2014",
doi = "10.1109/ISCAS.2014.6865588",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2129--2132",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",
}