An area- and power-efficient half-rate clock and data recovery circuit

Yen Long Lee, Soon Jyh Chang, Rong Sing Chu, Yen Chi Chen, Jih Ren Goh, Chung Ming Huang

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor reduces the power consumption and area in high-speed operation. This CDR circuit has been designed in TSMC 0.18 μm CMOS technology. It consumes 22.5 mW from a 1.8-V supply and occupies an active area of 0.26 mm 2. The peak-to-peak and rms jitter of the recovered clock are 95.6 ps and 12.1 ps for a 3.2 Gb/s 27-1 PRBS, respectively.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2129-2132
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 2014 一月 1
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 2014 六月 12014 六月 5

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家Australia
城市Melbourne, VIC
期間14-06-0114-06-05

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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