An area efficient gate-all-around ring MOSFET

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper proposes an area efficient gate-all-around ring (GAAR) MOSFET structure for vertical integration, which in essence is an arc-shaped double-gate FinFET and gains benefits of the superior gate control in GAA MOSFETs and feasible manufacturability. Such new structure offers another advantage of tunable performance by changing the size of the ring, giving a simple circuit design flexibility for various performance need for SoC application, especially for vertical transistors with the same gate length. It is shown that a 40% reduction in area is achieved using the vertical GAAR, as compared with conventional multi-fin MOSFETs.

原文English
主出版物標題2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面118-119
頁數2
ISBN(電子)9781509007264
DOIs
出版狀態Published - 2016 九月 27
事件21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States
持續時間: 2016 六月 122016 六月 13

出版系列

名字2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Other

Other21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
國家United States
城市Honolulu
期間16-06-1216-06-13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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