An area-efficient systolic division circuit over GF(2m) for secure communication

Chien Hsing Wu, Chien Ming Wu, Ming-Der Shieh, Yin Tsung Hwang

研究成果: Conference article

15 引文 (Scopus)

摘要

We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
出版狀態Published - 2002 一月 1
事件2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
持續時間: 2002 五月 262002 五月 29

指紋

Networks (circuits)
Secure communication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

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An area-efficient systolic division circuit over GF(2m) for secure communication. / Wu, Chien Hsing; Wu, Chien Ming; Shieh, Ming-Der; Hwang, Yin Tsung.

於: Proceedings - IEEE International Symposium on Circuits and Systems, 卷 5, 01.01.2002.

研究成果: Conference article

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T1 - An area-efficient systolic division circuit over GF(2m) for secure communication

AU - Wu, Chien Hsing

AU - Wu, Chien Ming

AU - Shieh, Ming-Der

AU - Hwang, Yin Tsung

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Y1 - 2002/1/1

N2 - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

AB - We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2m) based on the extended Stein's algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m2), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.

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