TY - GEN
T1 - An effective matrix compression method for GPU-accelerated thermal analysis
AU - Chiou, Lih Yih
AU - Lu, Liang Ying
AU - Lin, Chieh Yu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/5/28
Y1 - 2015/5/28
N2 - Three-dimensional integrated circuits are expected to face increasingly severe thermal challenges and cost issues as the number of stacked ICs increases. Thermal analysis for 3D ICs is urgently required to assist system designers at the early phase of design to identify hot zones. Most thermal analyses obtain detailed temperature distribution by large matrix operations, and hence reduce analysis performance. Accordingly, we propose a compressed and combined sparse row (CCSR) matrix format to be used in the proposed effective matrix compression (EMC) method for matrix multiplication on GPU. The experimental results show EMC using CCSR is on average 44.93 times faster than matrix multiplication without any special compression format and on average at least 3.09 times faster than other compression formats.
AB - Three-dimensional integrated circuits are expected to face increasingly severe thermal challenges and cost issues as the number of stacked ICs increases. Thermal analysis for 3D ICs is urgently required to assist system designers at the early phase of design to identify hot zones. Most thermal analyses obtain detailed temperature distribution by large matrix operations, and hence reduce analysis performance. Accordingly, we propose a compressed and combined sparse row (CCSR) matrix format to be used in the proposed effective matrix compression (EMC) method for matrix multiplication on GPU. The experimental results show EMC using CCSR is on average 44.93 times faster than matrix multiplication without any special compression format and on average at least 3.09 times faster than other compression formats.
UR - http://www.scopus.com/inward/record.url?scp=84936984417&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-DAT.2015.7114505
DO - 10.1109/VLSI-DAT.2015.7114505
M3 - Conference contribution
AN - SCOPUS:84936984417
T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Y2 - 27 April 2015 through 29 April 2015
ER -