An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays

Bin Da Liu; Kai Cheng Wei

doi:10.1109/81.298365

An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays

Bin Da Liu
, Kai Cheng Wei

電機工程學系

研究成果: Article › 同行評審

摘要

-Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.

原文	English
頁（從 - 到）	494-498
頁數	5
期刊	IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
卷	41
發行號	7
DOIs	https://doi.org/10.1109/81.298365
出版狀態	Published - 1994 7月

All Science Journal Classification (ASJC) codes

電氣與電子工程

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10.1109/81.298365

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@article{b866daaece88475a80e43cfc76609102,

title = "An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays",

abstract = "-Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.",

author = "Liu, \{Bin Da\} and Wei, \{Kai Cheng\}",

note = "Funding Information: Manuscript received February 8, 1993; revised October 20, 1993. This work was supported by the National Science Council, Republic of China, under Contract NSC-82-0404-E-00\&220. This paper was recommended by Associate Editor Isao Shirakawa. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, Republic of China. IEEE Log Number 9400333.",

year = "1994",

month = jul,

doi = "10.1109/81.298365",

language = "English",

volume = "41",

pages = "494--498",

journal = "IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications",

issn = "1057-7122",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays

AU - Liu, Bin Da

AU - Wei, Kai Cheng

N1 - Funding Information: Manuscript received February 8, 1993; revised October 20, 1993. This work was supported by the National Science Council, Republic of China, under Contract NSC-82-0404-E-00&220. This paper was recommended by Associate Editor Isao Shirakawa. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, Republic of China. IEEE Log Number 9400333.

PY - 1994/7

Y1 - 1994/7

N2 - -Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.

AB - -Different from the previous PLA folding algorithms which perform row and column foldings independently, we propose an algorithm to obtain bipartite row or column folding result on the same graph. The PLA personality matrix is modeled as a graph and the folding problem is modeled as a partitioning problem. Experimental results show that this algorithm can lead a good guide to select row or column folding for reducing the chip area of the PLA efficiently.

UR - https://www.scopus.com/pages/publications/0028464686

UR - https://www.scopus.com/pages/publications/0028464686#tab=citedBy

U2 - 10.1109/81.298365

DO - 10.1109/81.298365

M3 - Article

AN - SCOPUS:0028464686

SN - 1057-7122

VL - 41

SP - 494

EP - 498

JO - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

IS - 7

ER -

An Efficient Algorithm for Selecting Bipartite Row or Column Folding of Programmable Logic Arrays

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