An efficient design-for-testability scheme for 2-D transform in H.264 advanced video coders

Heng Yao Lin, Hui Hsien Tsai, Bin Da Liu, Jar Ferr Yang, Soon Jyh Chang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, an easily design-for-testability (DfT) scheme based on C-testability conditions is adopted to implement test syntheses of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC). The proposed testable scheme is applied to bit-level regular arrangement for the transform architecture. It guarantees 100% fault coverage while the resulting number of test pattern is only 8. The proposed integrated transforms have been synthesized with UMC 0.18 μm technology. Under the small performance degradation, simulation results show that the DfT implementation increases about only 12% area overhead compared with the original circuit.

原文English
主出版物標題APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
頁面255-258
頁數4
DOIs
出版狀態Published - 2006 十二月 1
事件APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
持續時間: 2006 十二月 42006 十二月 6

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
國家/地區Singapore
期間06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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