An efficient design of variable length decoder for MPEG-1/2/4

Pei Yin Chen, Yi Ming Lin, Min Yi Cho

研究成果: Article同行評審

摘要

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 μm process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

原文English
文章編號4668499
頁(從 - 到)1307-1315
頁數9
期刊IEEE Transactions on Multimedia
10
發行號7
DOIs
出版狀態Published - 2008 十一月

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 媒體技術
  • 電腦科學應用
  • 電氣與電子工程

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