TY - GEN
T1 - An efficient hybrid cache coherence protocol for shared memory multiprocessors
AU - Chang, Yeimkuan
AU - Bhuyan, L. N.
N1 - Funding Information:
*This research has been partly supported by NSF grant MIP-
Publisher Copyright:
© 1996 IEEE.
PY - 1996
Y1 - 1996
N2 - This paper presents a new tree-based cache coherence protocol which is a hybrid of the limited directory and the linked list schemes. By utilizing a limited number of pointers in the directory, the proposed protocol connects the nodes caching a shared block in a tree fashion. In addition to the low communication overhead, the proposed scheme also contains the advantages of the existing bit-map and tree-based linked list protocols, namely, scalable memory requirement and logarithmic invalidation latency. We evaluate the performance of our protocol by running four applications on an execution-driven simulator. Our simulation results show that the performance of the proposed protocol is very close to that of the full-map directory protocol.
AB - This paper presents a new tree-based cache coherence protocol which is a hybrid of the limited directory and the linked list schemes. By utilizing a limited number of pointers in the directory, the proposed protocol connects the nodes caching a shared block in a tree fashion. In addition to the low communication overhead, the proposed scheme also contains the advantages of the existing bit-map and tree-based linked list protocols, namely, scalable memory requirement and logarithmic invalidation latency. We evaluate the performance of our protocol by running four applications on an execution-driven simulator. Our simulation results show that the performance of the proposed protocol is very close to that of the full-map directory protocol.
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U2 - 10.1109/ICPP.1996.537158
DO - 10.1109/ICPP.1996.537158
M3 - Conference contribution
AN - SCOPUS:85019583860
T3 - Proceedings of the International Conference on Parallel Processing
SP - 172
EP - 179
BT - Architecture
A2 - Reeves, A.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th International Conference on Parallel Processing, ICPP 1996
Y2 - 12 August 1996 through 16 August 1996
ER -