An efficient multimode multiplier supporting AES and fundamental operations of public-key cryptosystems

Chen Hsing Wang, Chieh Lin Chuang, Cheng Wen Wu

研究成果: Article

19 引文 斯高帕斯(Scopus)

摘要

This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrixvector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 × 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2n) at a clock rate of 100 MHz, respectively. With 21930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.

原文English
文章編號5288547
頁(從 - 到)553-563
頁數11
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
18
發行號4
DOIs
出版狀態Published - 2010 四月 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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