An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation

Yu Guang Chen, Ing Chao Lin, Kun Wei Chiu, Cheng Hsuan Liu

研究成果: Article同行評審

摘要

High leakage power consumption has become a serious problem in modern IC designs. By isolating a circuit block that is not in use from the power supply, power gating has become one of the most effective ways to reduce leakage power. During the circuit wake-up process, turning on sleep transistors simultaneously may induce an excessive surge current, which will threaten signal integrity. To avoid significant surge currents, sleep transistor wake-up sequences should be carefully designed. On the other hand, PMOS sleep transistors may suffer from the Negative-Bias Temperature Instability (NBTI) effect, where the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence-based methods do not consider the NBTI effect, which may result in a longer or an unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel reconfigurable circuit structure that can reconfigure the wake-up sequence and a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstances and then dynamically reconfigures wake-up sequences at runtime based on an actual aging scenario (i.e. different months or years of aging). The experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 49.78% of the average wake-up time latency. In the meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is only about 0.27% with a larger benchmark.

原文English
頁(從 - 到)60-71
頁數12
期刊Integration, the VLSI Journal
80
DOIs
出版狀態Published - 2021 九月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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