An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters

Wei Cheng Lien, Kuen Jong Lee, Tong Yu Hsieh, Wee Lung Ang

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for high-performance circuits due to their small area overhead, low performance impact and simple control circuitry. However, previous work based on a single, fixed-order TRC often requires long test time to achieve high fault coverage and large storage space to store required control data and TRC seeds. In this paper, a novel programmable multiple-TRC-based on-chip test generation scheme is proposed to minimize both the required test time and test data volume. The scan path of a circuit under test is divided into multiple equal-length scan segments, each converted to a small-size TRC controlled by a programmable control logic unit. An efficient algorithm to determine the required seeds and the control vectors is developed. Experimental results on ISCAS'89, ITC'99 and IWLS'05 benchmark circuits show that, on average, the proposed scheme using only a single programmable TRC design can achieve 35.58%-98.73% reductions on the number of test application cycles with smaller storage data volume compared with previous work. When using more programmable TRC designs, 83.60%-99.59% reductions can be achieved with only slight increase on test data volume.

原文English
文章編號6559094
頁(從 - 到)1254-1264
頁數11
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
32
發行號8
DOIs
出版狀態Published - 2013 八月 5

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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