TY - GEN
T1 - An efficient VLSI architecture for convolutional code decoding
AU - Shiau, Yeu Horng
AU - Chen, Pei Yin
AU - Yang, Hung Yu
AU - Lin, Yi Ming
AU - Huang, Shi Gi
PY - 2010
Y1 - 2010
N2 - In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.
AB - In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.
UR - http://www.scopus.com/inward/record.url?scp=78751496384&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78751496384&partnerID=8YFLogxK
U2 - 10.1109/ISNE.2010.5669156
DO - 10.1109/ISNE.2010.5669156
M3 - Conference contribution
AN - SCOPUS:78751496384
SN - 9781424466948
T3 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
SP - 223
EP - 226
BT - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
T2 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010
Y2 - 18 November 2010 through 19 November 2010
ER -