An efficient VLSI architecture for convolutional code decoding

Yeu Horng Shiau, Pei-Yin Chen, Hung Yu Yang, Yi Ming Lin, Shi Gi Huang

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.

原文English
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面223-226
頁數4
DOIs
出版狀態Published - 2010 十二月 1
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
持續時間: 2010 十一月 182010 十一月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家/地區Taiwan
城市Kaohsiung
期間10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「An efficient VLSI architecture for convolutional code decoding」主題。共同形成了獨特的指紋。

引用此