An efficient VLSI architecture for edge filtering in H.264/AVC

Chung Ming Chen, Chung Ho Chen

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

In this paper, we study and analyze the computational complexity of H.264/AVC baseline profile decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, the operations of content activity check, and the edge filtering are known to be very time consuming in the embedded system. In order to reduce the memory reference and improve overall system performance, we proposed a new efficient VLSI architecture to accelerate the processing of deblocking filter. The proposed architecture is called "Adaptive Edge Filtering Operation (AEFO)," which could be embedded in a platform-based architecture as a co-processor. As a result, the performance of the embedded system using AEFO is 1.66 times faster than software implementation. Moreover, the number of total memory references for loading and storage is reduced by 34% and 36% respectively.

原文English
主出版物標題Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
編輯V.G. Oklobdzija
頁面118-122
頁數5
出版狀態Published - 2005 12月 1
事件Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 - Marina del Rey, CA, United States
持續時間: 2005 10月 242005 10月 26

出版系列

名字Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Other

OtherThird IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
國家/地區United States
城市Marina del Rey, CA
期間05-10-2405-10-26

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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