An efficient VLSI architecture for transform-based intra prediction in H.264/AVC

Heng Yao Lin, Kuan Hsien Wu, Bin Da Liu, Jar Ferr Yang

研究成果: Article同行評審

33 引文 斯高帕斯(Scopus)

摘要

In this paper, an efficient mode decision algorithm and a high throughput hardware architecture with eight-pixel parallelism for improving the H.264/advanced video coding intra coding efficiency are proposed. Based on the inherent features of the discrete cosine transform, the input block is first transformed and then analyzed to determine its texture directional tendency. A few candidate modes are chosen for cost calculation, which adopts the error model in the sum of absolute integer-transformed differences (SAITD). Experimental results show that the proposed intra prediction algorithm has lower peak signal-to-noise ratio degradation and bit-rate increment compared to other recent designs. Using the SAITD technique, the proposed mode decision algorithm is effectively integrated into intra prediction rather than being a preprocessing unit. For hardware implementation, the proposed intra prediction algorithm in the macroblock level is implemented for prediction computation, mode decision, and reconstruction loop units. The synthesis results show that the proposed architecture can achieve a 100 MHz operation frequency, allowing it to easily support the real-time requirements for video resolutions of up to the 16 source input format.

原文English
文章編號5433025
頁(從 - 到)894-906
頁數13
期刊IEEE Transactions on Circuits and Systems for Video Technology
20
發行號6
DOIs
出版狀態Published - 2010 六月

All Science Journal Classification (ASJC) codes

  • 媒體技術
  • 電氣與電子工程

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