An efficient wakeup design for energy reduction in high-performance superscalar processors

Engineering

• Reliability Availability and Maintainability (Reliability Engineering) 100%
• Computer Aided Manufacturing 80%
• Electric Power Utilization 60%
• Experimental Result 20%
• Microprocessor 20%
• Critical Path 20%
• Save Power 20%
• Clock Cycle 20%
• Hot Spot 20%
• Nanosecond 20%

Keyphrases

• RAM Design 50%
• Complex Instruction 25%
• Matching Circuit 25%
• High Performance Microprocessor 25%
• Scheduling Logic 25%
• RAM Cell 25%
• Dynamic Scheduler 25%

Computer Science

• Complex Instruction 25%
• High-Performance Microprocessor 25%