An electromigration study of novel 3D Cu stack-via interconnects for advanced high-density fan-out packaging

Novel Cu via interconnects connecting Cu redistribution lines (RDLs) was proposed as advanced fan-out chip on substrate (FOCoS) technology for high-density packaging. The advance in downsizing Cu interconnect structure causes a rising concern for electromigration reliability. In this study, the electromigration behavior and failure mechanism in a novel 3D Cu stack-via interconnect were reported for the first time. The Cu stack-via structures, composed of three vertically stacked Cu microvias, were subjected to electromigration experiments at 5.1 × 10⁵ A/cm² at 180 °C with opposite electron flow directions to investigate the anisotropic electromigration behavior on the microstructure and electrical performance. Divergent electromigration behavior was disclosed in the Cu stack-via with different electron flow directions. The failure mechanism of the upstream Cu stack-via was governed by a rapid electrical resistance rise at the end of current stressing due to the synergistic local current crowding and Joule heating effects, and the volume shrinkage due to phase transformation further caused the open-circuit failure. The failure mechanism of the downstream Cu stack-via was governed by a gradual electrical resistance rise due to the depletion of Ni diffusion barrier metallization and the subsequent Cu microvia phase transformation to high-resistivity Cu-Sn IMC phases. In this study, the design rules of the Ni metallization thickness required to prevent early Ni metallization depletion and the Cu stack-via configuration to prevent local current crowding for improved electromigration reliability will be investigated for further progress in the novel 3D Cu stack-via interconnect development.