High-performance embedded systems tend to use caches and memory hierarchy to speed up program execution. This increases DRAM idle time (inter-access time) and provides opportunity for reducing memory energy usage by performing memory state transition to a low-power mode. However, additional delay due to resynchronization may greatly increase the system response time. This work focuses on exploiting state transition techniques to reduce DRAM energy usage and also mitigating the penalty of resynchronization time. We propose a state transition technique based on address prediction that predicts the inter-access time between memory accesses. According to predicted inter-access time, the DRAM is directly put into a low-energy mode and transits back to the operation mode as the idle timer expires to avoid resynchronization overhead. Experiments using multimedia application show that the proposed scheme has achieved the best energy-delay performance than other previous policies.
|出版狀態||Published - 2004|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 2004 12月 6 → 2004 12月 9
|Other||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||04-12-06 → 04-12-09|
All Science Journal Classification (ASJC) codes