An Energy-Efficient Conditional Biasing Write Assist with Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM

Chi Ray Huang, Lih Yih Chiou

研究成果: Article同行評審

摘要

Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can effectively improve the write{min} of static random access memory (SRAM) cells. The energy overhead associated with such assists is considerable due to the switching activities on high capacitive nodes for every write operation. In this brief, a conditional biasing WA with built-in time-based write-margin-tracking is proposed to avoid unnecessary assist for energy saving. The biasing voltage for assisting the write procedure is only adjusted during write failures and remains unchanged for native write-success cells. Compared with conventional WAs, the proposed design can reduce write energy by 29%-34% with a similar area overhead. In addition, silicon measurements have demonstrated that the proposed assist is functional for near-threshold operations and{DDmin} is reduced to 0.4 V.

原文English
文章編號9448190
頁(從 - 到)1586-1590
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
29
發行號8
DOIs
出版狀態Published - 2021 八月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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