An energy-efficient dual-edge triggered level-converting flip-flop

Lih Yih Chiou, Shien Chun Lou

研究成果: Conference article同行評審

11 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a dual-edge triggered and dual-Vth level converting flip-flop (LCFF). The LCFF utilizes many energy-saving features that can be used in a multi-Vdd and multi-Vth system. A novel power-aware latch structure is designed to eliminate the internal power during transition. When operated in sleep mode, the power-aware latch will switch to low-leakage mode and still retain its data. Experimental results show that the proposed LCFF has the lowest PDP among compared FFs.

原文English
文章編號4252845
頁(從 - 到)1157-1160
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 2007
事件2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
持續時間: 2007 5月 272007 5月 30

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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