An enhanced double-TSV Scheme for defect tolerance in 3D-IC

Hsiu Chuan Shih, Cheng Wen Wu

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Die stacking based on Through-Silicon Via (TSV) is considered as an efficient way to reducing power consumption and form factor. In the current stage, the failure rate of TSV is still high, so some type of defect tolerance scheme is required. Meanwhile, the concept of double-via, which is normally used in traditional layer to layer interconnection, can be one of the feasible tolerance schemes. Double-via/TSV has a benefit compared to TSV repair: it can eliminate the fuse configuration procedure as well as the fuse layer. However, double-TSV has a problem of signal degradation and leakage caused by short defects. In this work, an enhanced scheme for double-TSV is proposed to solve the short-defect problem through signal path division and VDD isolation. Result shows that the enhanced double-TSV can tolerate both open and short defects, with reasonable area and timing overhead.

原文English
主出版物標題Proceedings - Design, Automation and Test in Europe, DATE 2013
頁面1486-1489
頁數4
出版狀態Published - 2013 十月 21
事件16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
持續時間: 2013 三月 182013 三月 22

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
ISSN(列印)1530-1591

Conference

Conference16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
國家/地區France
城市Grenoble
期間13-03-1813-03-22

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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