TY - GEN
T1 - An enhanced SRAM BISR design with reduced timing penalty
AU - Denq, Li Ming
AU - Wang, Tzu Chiang
AU - Wu, Cheng Wen
PY - 2006/12/1
Y1 - 2006/12/1
N2 - Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the Built-in Self-Test (BIST) circuit - only one multiplexer delay for both the inputs and outputs.
AB - Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the Built-in Self-Test (BIST) circuit - only one multiplexer delay for both the inputs and outputs.
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U2 - 10.1109/ATS.2006.260988
DO - 10.1109/ATS.2006.260988
M3 - Conference contribution
AN - SCOPUS:33947663032
SN - 0769526284
SN - 9780769526287
T3 - Proceedings of the Asian Test Symposium
SP - 25
EP - 30
BT - Proceedings of the 15th Asian Test Symposium 2006
T2 - 15th Asian Test Symposium 2006
Y2 - 20 November 2006 through 23 November 2006
ER -