An enhanced SRAM BISR design with reduced timing penalty

Li Ming Denq, Tzu Chiang Wang, Cheng Wen Wu

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the Built-in Self-Test (BIST) circuit - only one multiplexer delay for both the inputs and outputs.

原文English
主出版物標題Proceedings of the 15th Asian Test Symposium 2006
頁面25-30
頁數6
DOIs
出版狀態Published - 2006 十二月 1
事件15th Asian Test Symposium 2006 - Fukuoka, Japan
持續時間: 2006 十一月 202006 十一月 23

出版系列

名字Proceedings of the Asian Test Symposium
2006
ISSN(列印)1081-7735

Other

Other15th Asian Test Symposium 2006
國家Japan
城市Fukuoka
期間06-11-2006-11-23

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Hardware and Architecture

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