An enhancement-mode pseudomorphic high electron mobility transistor prepared by an Electroless Plating (EP) and a gate-sinking approaches

Chun Chia Chen, Huey-Ing Chen, I-Ping Liu, Po Cheng Chou, Jian Kai Liou, Jung Hui Tsai, Wen-Chau Liu

研究成果: Article

摘要

An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300-475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2 , the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.

原文English
頁(從 - 到)45-50
頁數6
期刊Solid-State Electronics
105
DOIs
出版狀態Published - 2015 一月 1

指紋

sinking
Electroless plating
High electron mobility transistors
high electron mobility transistors
plating
Threshold voltage
augmentation
Transconductance
Thermodynamic stability
threshold voltage
Drain current
Field effect transistors
transconductance
Atomic force microscopy
Modulation
Spectroscopy
thermal stability
Scanning electron microscopy
ambience
logic

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

引用此文

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abstract = "An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300-475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2 , the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.",
author = "Chen, {Chun Chia} and Huey-Ing Chen and I-Ping Liu and Chou, {Po Cheng} and Liou, {Jian Kai} and Tsai, {Jung Hui} and Wen-Chau Liu",
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T1 - An enhancement-mode pseudomorphic high electron mobility transistor prepared by an Electroless Plating (EP) and a gate-sinking approaches

AU - Chen, Chun Chia

AU - Chen, Huey-Ing

AU - Liu, I-Ping

AU - Chou, Po Cheng

AU - Liou, Jian Kai

AU - Tsai, Jung Hui

AU - Liu, Wen-Chau

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AB - An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300-475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2 , the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.

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