An error-tolerance-based test methodology to support product grading for yield enhancement

Tong Yu Hsieh, Kuen Jong Lee, Melvin A. Breuer

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel error-tolerance-based test methodology to grade defective chips according to their degree of acceptability so as to improve the effective yield of chips. We employ error rate as the attribute of error-tolerance to determine acceptability. We show that the number of test patterns that need to be applied to a circuit under test in estimating the circuit's error rate is highly dependent on how close the circuit's actual error rate is to the given grading thresholds. An iterative and adaptive error rate estimation technique is developed by which an appropriate number of test patterns can be efficiently determined and the circuit can be immediately classified into appropriate grades to fit various application requirements. Experimental results show that: 1) only a few iterations are required to classify a circuit, and 2) the total number of test patterns used is in general independent of the circuit size. Both of these observations imply that these techniques are applicable to large circuits.

原文English
文章編號5768131
頁(從 - 到)930-934
頁數5
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
30
發行號6
DOIs
出版狀態Published - 2011 六月

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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