An error tolerance scheme for 3D CMOS imagers

Hsiu Ming Chang, Jiun Lang Huang, Ding Ming Kwai, Kwang Ting Cheng, Cheng Wen Wu

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)


A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using micro-bumps (μbumps) and through-silicon vias (TSVs) is promising for high throughput applications. However, due to the direct mapping from pixels to ISPs, the overall yield relies heavily on the correctness of the μbumps, ADCs and TSVs - a single defect leads to the information loss of a tile of pixels. This paper presents an error tolerance scheme for the 3D CMOS imager that can still deliver high quality images in the presence of μbump, ADC, and/or TSV failures. The error tolerance is achieved by properly interleaving the connections from pixels to ADCs so that the corrupted data, if any, can be recovered in the ISPs. A key design parameter, the interleaving stride, is decided by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3D imager from 46% to 99%.

主出版物標題Proceedings of the 47th Design Automation Conference, DAC '10
出版狀態Published - 2010 九月 7
事件47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
持續時間: 2010 六月 132010 六月 18


名字Proceedings - Design Automation Conference


Other47th Design Automation Conference, DAC '10
國家/地區United States
城市Anaheim, CA

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 控制與系統工程
  • 電氣與電子工程
  • 建模與模擬


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