An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Yu Feng Hsieh, Si Hua Chen, Nan Yow Chen, Wen Jay Lee, Jyun Hwei Tsai, Chun Nan Chen, Meng Hsueh Chiang, Darsen D. Lu, Kuo Hsing Kao

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage (Vth) roll-off can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the Vth roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.

原文English
頁(從 - 到)855-859
頁數5
期刊IEEE Transactions on Electron Devices
65
發行號3
DOIs
出版狀態Published - 2018 3月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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