An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Chih Sheng Hou, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)

摘要

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

原文English
主出版物標題2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
出版狀態Published - 2013 八月 15
事件2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
持續時間: 2013 四月 222013 四月 24

出版系列

名字2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
國家/地區Taiwan
城市Hsinchu
期間13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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