An HMAC processor with integrated SHA-1 and MD5 algorithms

Mao Yin Wang, Chih Pin Su, Chih Tsun Huang, Cheng Wen Wu

研究成果: Paper

38 引文 (Scopus)

摘要

Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost - 12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.

原文English
頁面456-458
頁數3
出版狀態Published - 2004 六月 1
事件Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
持續時間: 2004 一月 272004 一月 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
國家Japan
城市Yokohama
期間04-01-2704-01-30

指紋

Hardware
Hash functions
Silicon
Communication
Costs

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

引用此文

Wang, M. Y., Su, C. P., Huang, C. T., & Wu, C. W. (2004). An HMAC processor with integrated SHA-1 and MD5 algorithms. 456-458. 論文發表於 Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.
Wang, Mao Yin ; Su, Chih Pin ; Huang, Chih Tsun ; Wu, Cheng Wen. / An HMAC processor with integrated SHA-1 and MD5 algorithms. 論文發表於 Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.3 p.
@conference{5bc752fa95254003a3e22d89716fbefe,
title = "An HMAC processor with integrated SHA-1 and MD5 algorithms",
abstract = "Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost - 12.5{\%} by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.",
author = "Wang, {Mao Yin} and Su, {Chih Pin} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",
year = "2004",
month = "6",
day = "1",
language = "English",
pages = "456--458",
note = "Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 ; Conference date: 27-01-2004 Through 30-01-2004",

}

Wang, MY, Su, CP, Huang, CT & Wu, CW 2004, 'An HMAC processor with integrated SHA-1 and MD5 algorithms', 論文發表於 Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan, 04-01-27 - 04-01-30 頁 456-458.

An HMAC processor with integrated SHA-1 and MD5 algorithms. / Wang, Mao Yin; Su, Chih Pin; Huang, Chih Tsun; Wu, Cheng Wen.

2004. 456-458 論文發表於 Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.

研究成果: Paper

TY - CONF

T1 - An HMAC processor with integrated SHA-1 and MD5 algorithms

AU - Wang, Mao Yin

AU - Su, Chih Pin

AU - Huang, Chih Tsun

AU - Wu, Cheng Wen

PY - 2004/6/1

Y1 - 2004/6/1

N2 - Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost - 12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.

AB - Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost - 12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.

UR - http://www.scopus.com/inward/record.url?scp=2442611804&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2442611804&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:2442611804

SP - 456

EP - 458

ER -

Wang MY, Su CP, Huang CT, Wu CW. An HMAC processor with integrated SHA-1 and MD5 algorithms. 2004. 論文發表於 Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.