TY - GEN
T1 - An Improved Dynamic Hash Table on GPU with Configurable on-Chip Memory
AU - Chang, Yeim Kuan
AU - Chuang, Chu Chia
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Hash tables are crucial data structures used for efficient storage and retrieval of data, finding wide applications in various domains such as computer graphics, machine learning, traffic tracking, and database queries. The main objective of this paper is to implement a dynamic hash table that achieves high throughput and operates in parallel. We propose a technique for data-parallel hashing using graphics processing units (GPU) and improve upon the dynamic hash table by leveraging the configurable on-chip memory on GPU. This approach enables high-throughput data insertion, search, and deletion while adhering to the real-world 80/20 rule. We utilize the programming techniques provided by NVIDIA CUDA, minimizing memory access through well-designed data structures. Atomic operations ensure the absence of race conditions, and cooperative groups maximize the utilization of GPU threads, achieving optimal parallel computation. The GPU executes hash table operations in parallel by employing the SIMT (Single Instruction, Multiple Threads) mechanism. Furthermore, we enhance existing data-parallel hashing techniques on GPU to address the challenge of decreasing throughput when the same keys are frequently updated in the hash table. Our architecture significantly improves upon this issue and efficiently handles scenarios in which 20% of elements occupy 80% of the frequency in the real world, even in cases of frequent duplicate key insertions or updates. Additionally, we adopt the LRU (Least Recently Used) approach to keep frequently queried data in the configurable on-chip memory, ensuring that important and frequently requested information is readily accessible. According to the experimental results, our proposed method, under the real-world 80/20 rule, achieves an 82.64 times improvement in insertion throughput compared to the state-of-the-art parallel hashing techniques on GPU. Also, the search throughput is increased by 5 to 8%.
AB - Hash tables are crucial data structures used for efficient storage and retrieval of data, finding wide applications in various domains such as computer graphics, machine learning, traffic tracking, and database queries. The main objective of this paper is to implement a dynamic hash table that achieves high throughput and operates in parallel. We propose a technique for data-parallel hashing using graphics processing units (GPU) and improve upon the dynamic hash table by leveraging the configurable on-chip memory on GPU. This approach enables high-throughput data insertion, search, and deletion while adhering to the real-world 80/20 rule. We utilize the programming techniques provided by NVIDIA CUDA, minimizing memory access through well-designed data structures. Atomic operations ensure the absence of race conditions, and cooperative groups maximize the utilization of GPU threads, achieving optimal parallel computation. The GPU executes hash table operations in parallel by employing the SIMT (Single Instruction, Multiple Threads) mechanism. Furthermore, we enhance existing data-parallel hashing techniques on GPU to address the challenge of decreasing throughput when the same keys are frequently updated in the hash table. Our architecture significantly improves upon this issue and efficiently handles scenarios in which 20% of elements occupy 80% of the frequency in the real world, even in cases of frequent duplicate key insertions or updates. Additionally, we adopt the LRU (Least Recently Used) approach to keep frequently queried data in the configurable on-chip memory, ensuring that important and frequently requested information is readily accessible. According to the experimental results, our proposed method, under the real-world 80/20 rule, achieves an 82.64 times improvement in insertion throughput compared to the state-of-the-art parallel hashing techniques on GPU. Also, the search throughput is increased by 5 to 8%.
UR - https://www.scopus.com/pages/publications/105018736118
UR - https://www.scopus.com/pages/publications/105018736118#tab=citedBy
U2 - 10.1109/ICUFN65838.2025.11170098
DO - 10.1109/ICUFN65838.2025.11170098
M3 - Conference contribution
AN - SCOPUS:105018736118
T3 - International Conference on Ubiquitous and Future Networks, ICUFN
SP - 582
EP - 587
BT - ICUFN 2025 - 16th International Conference on Ubiquitous and Future Networks
PB - IEEE Computer Society
T2 - 16th International Conference on Ubiquitous and Future Networks, ICUFN 2025
Y2 - 8 July 2025 through 11 July 2025
ER -