With the fast development pace of deep submicron technology, the size and density of semiconductor memory grows rapidly. However, keeping a high level of yield and reliability for memory products is more and more difficult. Both the redundancy repair and ECC techniques have been widely used for enhancing the yield and reliability of memory chips. Specifically, the redundancy repair and ECC techniques are conventionally used to repair or correct the hard faults and soft errors, respectively. In this paper, we propose an integrated ECC and redundancy repair scheme for memory reliability enhancement. Our approach can identify the hard faults and soft errors during the memory normal operation mode, and repair the hard faults during the memory idle time as long as there are unused redundant elements. We also develop a method for evaluating the memory reliability. Experimental results show that the proposed approach is effective, e.g., the MTTFof an 32K × 64 memory is improved by 1,412 hours (7.1%) with our integrated ECC and repair scheme.
|頁（從 - 到）||81-89|
|期刊||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|出版狀態||Published - 2005 十二月 12|
|事件||20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005 - Monterey, CA, United States|
持續時間: 2005 十月 3 → 2005 十月 5
All Science Journal Classification (ASJC) codes
- 工程 (全部)